(a) Field of the Invention
This invention relates to improvements in a semiconductor device, particularly a semiconductor device, in which a groove formed in a semiconductor substrate and having side wall surfaces perpendicular to the principal surface of the substrate is utilized for an element isolation region, a capacitor element, etc., and also a method of manufacturing the same.
(b) Description of the Prior Art
In order to enhance the integration density of the semiconductor integrated circuit device, it has been in practice to form a semiconductor substrate with a groove having groove walls perpendicular to the principal surface of the substrate, cover the groove surface with an insulating film and use this region for element separation or capacitance element or the like. The groove having walls perpendicular to the principal surface of the substrate as noted above, is formed by anisotropic etching, e.g., RIE (reactive ion etching).
FIG. 1 shows an example of application of this method to the separation of a well region in a CMOS from a substrate region. Referring to the Figure, reference numeral 1 designates an n-type silicon substrate, in which a p-type well region (p-type well) 2 is formed. A groove surrounding the p-type well 2 is formed, and a silicon oxide film 3 is formed in the groove. An n-channel MOS transistor 4 is formed in the p-type well 2, and a p-channel MOS transistor 5 is formed in the n-type substrate region. By isolating the p-type well 2 and n-type substrate region 1 from each other with the insulating layer 3, it is possible to suppress operation of a lateral parasitic bipolar transistor that is present between the p-type well 2 and n-type substrate region 1, thus preventing the phenomenon of latch-up. It is thus possible to reduce the distance between the p-type channel MOS transistor 4 and n-type channel MOS transistor 5 to improve the integration density.
FIG. 2 shows an example of application of the groove formation method noted above to a DRAM memory cell capacitor element. Referring to the Figure, reference numeral 11 designates a p-type silicon substrate. A field oxide film 12 is formed by a selective oxidation process on the surface of the silicon substrate 11, which isolates a surrounded memory cell region. A groove having a rectangular sectional profile is formed by the RIE process in the memory cell region, and an electrode 14 consisting of a polycrystalline silicon layer is formed over the groove surface via a thermal oxide film 13. An n-type impurity region 15 is formed by doping the silicon substrate 11 with an n-type impurity from the wall surface of the groove. A DRAM capacitor element is constituted by the n-type impurity region 15, thermal oxide film 13 and polycrystalline silicon electrode 14. Reference numeral 16 designates a transfer transistor of the DRAM memory cell, with the drain region of the transfer transistor being contiguous to the n-type impurity region 15 of the capacitor element. By forming the capacitor element by making use of the groove wall surface of the groove, it is possible to reduce the element area exclusively occupied by the capacitor element and hence increase the integration density.
The method of improving the integration density by making use of a groove having walls perpendicular to the principal surface of the substrate as described above, also finds extensive applications to resistor elements and ordinary element isolation.
As shown in FIG. 3, a silicon substrate 21 which is used for the manufacture of a semiconductor device is wafer-like (hereinafter referred to as silicon wafer), the principal surface of which is constituted by crystal plane (100) of plane orientation. The silicon wafer has an orientation flat 22 of crystal plane (110) perpendicular to the principal surface. When manufacturing a semiconductor device shown in FIGS. 1 and 2, the groove 23 used for a capacitor element or isolation region, is formed to extend in a direction parallel to or perpendicular to the orientation flat 22. This is done so because the circuit patterns concerned are formed by computer processing, and it is rather difficult to deal with lines which are neither parallel or perpendicular to the orientation flat as computer data.
With the groove 23 formed to extend in a direction parallel or perpendicular to the orientation flat 22, all the groove wall surfaces perpendicular to the principal surface of the silicon wafer 21 are constituted by crystal plane (110), while the groove bottom surface which is parallel to the principal surface, is constituted by crystal plane (100).
The fact that the exposed surfaces of the groove used for the formation of a capacitor element or a element isolation region are constituted by crystal plane (100) at the bottom and crystal plane (110) at sides perpendicular to the bottom, poses problems.
A first problem is that in case of a CMOS the possibility of latch-up due to current leak is increased with increasing integration density in spite of the presence of the groove-like insulating isolation region.
A second problem is that in case of a capacitor element of a DRAM memory cell as noted above the breakdown voltage of the portion where the groove is formed is deteriorated with increase of the integration density.